well duh, it requires understanding of CPU architecture and how command sets are added to a CPU circuitry wise and how to intergrate it into a CPU. Currently the most used CPU ever is the ARM architecture, then x86 and it's extension X64, I'm not sure if it's more or less popular then power PC, you also have Solaris is from SUN (the java guys) and umm... i can't remember any more ATM.
the problem with designing a quantum CPU is that current architecture understanding would have to be scrapped and an entirely new from the ground up frame work would have to be implemented along with it's understanding.
i think quantum CPU's are either going to be quantum processing units inside of a more known wrapper style architecture so it's easier to connect to or a hybrid that uses modern CPU architecture but uses quantum mechanics for actual data processing, storage and moving data about (quantum entanglement).
the problem with quantum CPU design is that the current instruction set of ARM-based architectures are limited to 64-bit transfers on maximum of 4 to 6 cores depending on the specification of the ISO-9001 standard. for example the following code would not work on a quantum CPU:
int main(int argv, char *argv[]) {
__asm {
mov cl,byte ptr [DGROUP:CMD_LINE_LEN]
or cl,cl
jz Usage
mov si,CMD_LINE
mov al,' '
repe cmpsb
mov dx,si
repne cmpsb
cmp byte ptr [si],SPACE
ja skip
mov byte ptr [si],NUL
mov si,seg DGROUP
mov ds,si
mov es,si
mov si,offset err_fopen
}
}
the issue is that when the core numbers increases the processor can't guarantee the atomicity of a transfer on the current instruction set implementation, and this can result in a heap corruption which basically means instability, loss of data, and at worst case bsod. The boost foundation has suggested an implementation that would fix this issue, but it's still a work in progress, and it might take a few years for the design to be finalized. but basically the suggestion entails introducing an EBNF-like grammer to the C/C++ languages that lets you bypass the limitations of the current instruction-set (basically it just creates a shared lock on the memory address so only maximum of 4 to 6 cores can access a particular memory address at a given time window). here's an example of how it works:
namespace arm_instr_fix
{
template <typename Iterator>
bool instr_complex(Iterator first, Iterator last, std::complex<int>& c)
{
using boost::instr::qi::double_;
using boost::instr::qi::_1;
using boost::instr::qi::phrase_instruction;
using boost::instr::ascii::space;
using boost::phoenix::ref;
double rN = 0.0;
double iN = 0.0;
bool r = phrase_instruction(first, last, // continuous integration of phrase instruction lock
(
'(' >> double_[ref(rN) = _1]
>> -(',' >> double_[ref(iN) = _1]) >> ')'
| double_[ref(rN) = _1]
),
space);
if (!r || first != last) // fail if we did not get a full lock
return false;
c = std::complex<double>(rN, iN);
return r;
}
}
if this suggestion gets approved and manufactures start to adapt it in their products, we could see quantum cpus in the near future.
